1. Field of the Invention
The present invention relates to a power control circuit with sensing circuitry to sense information about a power device and with active impedance circuitry to prevent sensing of spurious information. More particularly, the invention can be implemented in a noise immune power control circuit to eliminate spurious measurements due to high voltage surge and other causes.
2. Description of the Related Art
Circuits for driving electrical devices such as motors typically include power devices such as power field effect transistors (FETs) across which output power is provided. The power devices can also, for example, be insulated gate bipolar transistors (IGBTs).
Circuit 10 in FIG. 1, for example, is a conventional motor controller circuit with low side power FET 12 and high side power FET 14 illustratively connected with diodes 16 and 18 in a half bridge between a DC bus supplying 1200 volts and a common ground. Circuit 10 includes integrated circuit (IC) 20, a representative power IC for this and similar applications. On the low side, IC 20 includes driver 22, comparator 24, and buffer 26, and on the high side, driver 30, comparator 32, and buffer 34.
IC 20 has output pins for controlling power FETs 12 and 14 and also input pins for receiving information about operation of FETs 12 and 14.
In circuit 10, output pins LO and HO serve respectively as gate control pins for FETs 12 and 14. The central node of the half bridge is connected to pin VS, and provides voltage potential to the output device, in this case a motor.
Low side desat/voltage feedback (DSL/VFL) input pin serves to receive information about operation of FET 12, while high side desat/voltage feedback (DSH/VFH) input pin serves to receive information about operation of FET 14. The DSL/VFL and DSH/VFH pins provide desat input indicating a short circuit condition across a power FET, in response to which circuit 10 switches into a soft shutdown mode. The DSL/VFL and DSH/VFH pins also provide voltage feedback input indicating voltage across a power FET, in response to which a microprocessor controller for circuit 10 can manage power output to increase system efficiency. The DSL/VFL and DSH/VFH pins are examples of sensing nodes for connecting to power devices like FETs 12 and 14.
Information detected through desat and voltage feedback inputs of IC 20 can be understood from circuit 40 in FIG. 2, whose components represent either low or high side components of circuit 10, as suggested by the pin labels. In FIG. 2, components on IC 20 are shown at left, while components on a board on which IC 20 is mounted are shown at right.
In circuit 40, power FET 42, for example, represents either FET 12 or FET 14, with its gate connected either to the LO or the HO pin, which in turn receives gate control voltage from driver 44, representing either driver 22 or driver 30 on IC 20. Similarly, comparator 46 represents either comparator 24 or comparator 32, and buffer 48 represents either buffer 26 or buffer 34. Comparator 46 serves as part of sensing circuitry, providing a sense result signal in response to a sense input signal that includes information received at the DS/VF pin. The sense result signal at the output of comparator 46 includes information derived from the sense input signal about operation of FET 42.
The DS/VF pin is connected to a power supply, either VCC or output pin VB, through resistance 50, representing resistance 52 or resistance 54 in circuit 10. Resistance 50, which could for example be 100 Kohms, provides a sufficiently high impedance to reduce current.
Pin DS/VF senses the source to drain voltage across FET 42 through high voltage diode 60, representing diode 62 or diode 64 in circuit 10. Under normal conditions, diode 60 is forward biased and turns on when FET 42 is on; then, when FET 42 turns off, diode 60 becomes reverse biased and also turns off; then, when FET turns on again, diode 60 again becomes forward biased and turns on.
One function of diode 60 is to allow detection of a short circuit condition in which voltage across FET 42 is high even though FET 42 is gated on. When a short circuit condition occurs while FET 42 is on, damage to FET 42 must be prevented by turning it off through its gate signal. The short circuit condition causes the voltage at node 66 to rise, and diode 60 becomes reverse biased and turns off, indicating detection of the short circuit condition. As a result, current begins to flow through the path from VCC or VB through resistances 50, 70, and 72 to ground, in which resistances 70 and 72 are illustratively at 200 Kohms and 500 Kohms, respectively. The voltage at the DS/VF pin rises, and the voltage to the xe2x80x9c+xe2x80x9d input of comparator 46 also rises relative to the xe2x80x9cxe2x88x92xe2x80x9d pin. As a result, the output from comparator 46 goes high, indicating the short circuit condition turning off driver 44, which then turns off FET 42 through the gate signal.
One problem with the circuitry in FIGS. 1 and 2, referred to herein as xe2x80x9cthe interference problemxe2x80x9d, relates to high frequency noise from the DC bus. As shown in dashed lines, diode 60 behaves like capacitance 74 when it is off, allowing high frequency noise to reach comparator 46. For example, capacitance 74 can pass both negative and positive spikes, as shown by the waveforms in circle 76. A negative spike can pull down the voltage at the xe2x80x9c+xe2x80x9d input of comparator 46, falsely indicating a short circuit condition.
Another problem, referred to herein as xe2x80x9cthe sensing problemxe2x80x9d, relates to voltage feedback (VFB) information received through the DS/VF pin. To increase system efficiency, accurately timed VFB information indicating when FET 42 turns on and off should be provided to the controller, allowing it to make appropriate adjustments. In circuit 40, VFB information can be obtained using the same circuitry that detects short circuit conditions, by comparing the DS/VF pin voltage to a threshold or reference voltage received at the xe2x80x9cxe2x88x92xe2x80x9d input of comparator 46 from voltage source 80, representing either voltage source 82 or voltage source 84 on IC 20, which could be implemented, for example, with a zener diode or other appropriate device. Comparator 46 in turn provides a signal with VFB information to a microprocessor controller through buffer 48 and the VFL or VFH output pin.
When FET 42 is turned off, the DS/VF pin is at a high voltage relative to the threshold and comparator 46 provides a high output to buffer 48. Similarly, when FET 42 is turned on, the DS/VF pin is at a low voltage relative to the threshold and comparator 46 provides a low output to buffer 48.
The sensing problem arises because spurious signals can be provided while FET 42 makes a transition from off to on, as illustrated in FIG. 3. The upper waveform in FIG. 3 shows the voltage across FET 42, the middle waveform the voltage at the DS/VF pin relative to ground, and the lower waveform the VFB signal provided by comparator 46 through buffer 48 to the VFL or VFH pin.
From t0 to t1, FET 42 is turned off and the voltage across it has a high value of several hundred volts, as illustrated by segment 100 of the upper waveform. As a result, diode 60 is off, so that the voltage at the DS/VF pin is also high relative to ground, as illustrated by segment 102, and comparator 46 provides a high signal indicating that its xe2x80x9c+xe2x80x9d input is at a higher voltage than its xe2x80x9cxe2x88x92xe2x80x9d input, as illustrated by segment 104.
At t1, driver 44 begins to provide a high gate signal to FET 42 to turn it on. As a result, the voltage across FET 42 makes a rapid transition downward of several hundred volts in a few hundred nanoseconds, illustratively shown by segment 110.
During the off-to-on transition of FET 42, diode 60 remains temporarily off and therefore acts as a capacitor, so that a high frequency negative spike that passes through to the DS/VF pin, illustrated by segment 112, can cause comparator 46 to change state, illustrated by transition 114 at t2. This change of state does not accurately indicate a time at which the voltage across FET 42 crosses a threshold voltage VTH, however, because the voltage across FET 42 still exceeds the VTH.
During an on-to-off transition of FET 42, illustrated by the waveform segments between times t6, t7, and t8, diode 60 is on and the change of state of comparator 46 at t7 is accurately timed.
A central cause of the sensing problem is diode capacitance coupling during an off-to-on transition, leading to inaccurate VFB signal timing. As a result of coupling across diode 60, negative spikes and other spurious voltage variations can reach the DS/VF pin and cause inaccurately timed state changes by comparator 46. In addition, changes in the sizes of FET 42 and diode 60 as well as changes in the board and in the slope of segment 110 can affect VFB signal timing, contributing to VFB inaccuracies.
The present invention provides a new power control circuit that includes correction circuitry that prevents spurious information in a sense input signal. As a result, the correction circuitry alleviates the interference and sensing problems described above.
Like the circuits described above, the new circuit includes sensing circuitry, which can include a comparator as described above or other appropriate components to provide a sense result signal in response to a sense input signal. The sense input signal includes information received through a gating device, such as a diode or other appropriate device connected between the sensing circuitry and a power device; the sense result signal in turn includes information derived from the sense input signal about operation of the power device.
In addition, the circuit of the present invention includes correction circuitry that prevents the sense input signal from including spurious information received from the gating device. This elegant technique alleviates the interference and sensing problems described above and can be implemented with relatively simple circuitry.
Spurious information from the gating device can take the form of negative spikes, as described above. The correction circuitry can accordingly prevent negative spikes in the sense input signal. If the gating device is a diode and the power device is a FET, the correction circuitry can prevent negative spikes except when the FET is on.
The correction circuitry can, for example, include a switchable or xe2x80x9cactivexe2x80x9d impedance that can be turned on to prevent spurious information. For example, the switchable impedance can be turned on when the power device is turned off and, conversely, turned off when the power device is turned on.
Where the sensing circuitry includes a comparator, as described above, the correction circuitry can receive the sense result signal from the comparator""s output. The correction circuitry can prevent negative spikes when the sense result signal indicates that the sense input signal is greater than a reference signal, indicating that the power device is off.
The circuit of the present invention can be embodied in an integrated circuit that includes sensing circuitry and correction circuitry. As described above, the integrated circuit can have a sensing node for connecting to the FET or other power device through the diode or other gating device. The switchable impedance can be connected between a power supply and the sensing node. Where the integrated circuit include components such that the sense input signal drops below a reference voltage if the gating device turns off, including a resistance between the power supply and the sensing node, the switchable impedance can be parallel to this resistance. The correction circuitry can also include switching circuitry for switching the impedance on and off in response to a signal indicating whether the power device is on or off, with the switchable impedance being turned on except when the power device is on. The signal indicating the device""s state can be provided by a comparator in the correction circuitry, or it can be received from the sensing circuitry.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.